A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.

Hiroki Morimura Satoshi Shigematsu Shinsuke Konaka A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. 12-17 1999 conf/islped/1999 ISLPED http://doi.acm.org/10.1145/313817.313829 db/conf/islped/islped1999.html#MorimuraSK99