BibTeX record conf/islped/LinYLCCHCSH12

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@inproceedings{DBLP:conf/islped/LinYLCCHCSH12,
  author       = {Yi{-}Wei Lin and
                  Hao{-}I Yang and
                  Geng{-}Cing Lin and
                  Chi{-}Shin Chang and
                  Ching{-}Te Chuang and
                  Wei Hwang and
                  Chia{-}Cheng Chen and
                  Willis Shih and
                  Huan{-}Shun Huang},
  editor       = {Naresh R. Shanbhag and
                  Massimo Poncino and
                  Pai H. Chou and
                  Ajith Amerasekera},
  title        = {A 55nm 0.55v 6T {SRAM} with variation-tolerant dual-tracking word-line
                  under-drive and data-aware write-assist},
  booktitle    = {International Symposium on Low Power Electronics and Design, ISLPED'12,
                  Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
  pages        = {79--84},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2333660.2333682},
  doi          = {10.1145/2333660.2333682},
  timestamp    = {Tue, 06 Nov 2018 16:59:21 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/LinYLCCHCSH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}