Reduction of minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic circuits with post-fabrication automatically selective charge injection.

Kentaro Honda Katsuyuki Ikeuchi Masahiro Nomura Makoto Takamiya Takayasu Sakurai Reduction of minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic circuits with post-fabrication automatically selective charge injection. 175-180 2011 ISLPED http://portal.acm.org/citation.cfm?id=2016847&CFID=34981777&CFTOKEN=25607807 conf/islped/2011 db/conf/islped/islped2011.html#HondaINTS11