<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/islped/HirakiBKGNSSS96" mdate="2006-02-15">
<author>Mitsuru Hiraki</author>
<author>Raminder Singh Bajwa</author>
<author>Hirotsugu Kojima</author>
<author>Douglas J. Gorny</author>
<author>Ken-ichi Nitta</author>
<author>Avadhani Shridhar</author>
<author>Katsuro Sasaki</author>
<author>Koichi Seki</author>
<title>Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.</title>
<pages>353-358</pages>
<year>1996</year>
<crossref>conf/islped/1996</crossref>
<booktitle>ISLPED</booktitle>
<ee>http://doi.acm.org/10.1145/252493.252634</ee>
<url>db/conf/islped/islped1996.html#HirakiBKGNSSS96</url>
</inproceedings>
</dblp>
