12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.

Hiroshi Fuketa Koji Hirairi Tadashi Yasufuku Makoto Takamiya Masahiro Nomura Hirofumi Shinohara Takayasu Sakurai 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. 163-168 2011 ISLPED http://portal.acm.org/citation.cfm?id=2016845&CFID=34981777&CFTOKEN=25607807 conf/islped/2011 db/conf/islped/islped2011.html#FuketaHYTNSS11