BibTeX record conf/isie/BranchiniFRMRVA17

• > Home > conf/isie/BranchiniFRMRVA17

@inproceedings{DBLP:conf/isie/BranchiniFRMRVA17,
  author       = {Paolo Branchini and
                  Andrea Fabbh and
                  Domenico Riondino and
                  Luigi Mariucci and
                  Matteo Rapisarda and
                  Antonio Valletta and
                  Alberto Aloisio and
                  Francesco Di Capua},
  title        = {Logic gates and memory elements design and simulation using {PMOS}
                  organic transistor},
  booktitle    = {26th {IEEE} International Symposium on Industrial Electronics, {ISIE}
                  2017, Edinburgh, United Kingdom, June 19-21, 2017},
  pages        = {2097--2101},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISIE.2017.8001580},
  doi          = {10.1109/ISIE.2017.8001580},
  timestamp    = {Thu, 14 Oct 2021 10:09:41 +0200},
  biburl       = {https://dblp.org/rec/conf/isie/BranchiniFRMRVA17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}