BibTeX record conf/ises/SurajWR22

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@inproceedings{DBLP:conf/ises/SurajWR22,
  author       = {Alavala Venkata Suraj and
                  Shaik Mohammed Waseem and
                  Subir Kumar Roy},
  title        = {Resource Constrained Hardware Architecture for Training Deep Neural
                  Networks at the Edge - {FPGA} Implementation},
  booktitle    = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2022,
                  Warangal, India, December 18-22, 2022},
  pages        = {358--361},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/iSES54909.2022.00079},
  doi          = {10.1109/ISES54909.2022.00079},
  timestamp    = {Sat, 02 Sep 2023 13:09:51 +0200},
  biburl       = {https://dblp.org/rec/conf/ises/SurajWR22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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