![](https://dblp.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
default search action
BibTeX record conf/ises/KambleSPVK18
@inproceedings{DBLP:conf/ises/KambleSPVK18, author = {Chetan Kamble and Siddharth R. K. and Shivnarayan Patidar and M. H. Vasantha and Nithin Y. B. Kumar}, title = {Design of Area-Power-Delay Efficient Square Root Carry Select Adder}, booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018}, pages = {80--85}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/iSES.2018.00026}, doi = {10.1109/ISES.2018.00026}, timestamp = {Mon, 03 Jan 2022 22:28:45 +0100}, biburl = {https://dblp.org/rec/conf/ises/KambleSPVK18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.