BibTeX record conf/ises/JoshiPA17

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@inproceedings{DBLP:conf/ises/JoshiPA17,
  author       = {Rathin K. Joshi and
                  Rutu Parekh and
                  Yash Agrawal},
  title        = {Design and Optimization of Single Electron Transistor Based 4-Bit
                  Arithmetic and Logic Unit at Room Temperature Operation},
  booktitle    = {{IEEE} International Symposium on Nanoelectronic and Information Systems,
                  iNIS 2017, Bhopal, India, December 18-20, 2017},
  pages        = {34--39},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.ieeecomputersociety.org/10.1109/iNIS.2017.17},
  doi          = {10.1109/INIS.2017.17},
  timestamp    = {Tue, 26 Dec 2023 20:25:46 +0100},
  biburl       = {https://dblp.org/rec/conf/ises/JoshiPA17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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