BibTeX record conf/ised/BanerjeeRR16

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@inproceedings{DBLP:conf/ised/BanerjeeRR16,
  author       = {Suchandra Banerjee and
                  Anand Ratna and
                  Suchismita Roy},
  title        = {Satisfiability modulo theory based methodology for floorplanning in
                  {VLSI} circuits},
  booktitle    = {Sixth International Symposium on Embedded Computing and System Design,
                  {ISED} 2016, Patna, India, December 15-17, 2016},
  pages        = {91--95},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISED.2016.7977061},
  doi          = {10.1109/ISED.2016.7977061},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/ised/BanerjeeRR16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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