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BibTeX record conf/iscas/ZhouL07
@inproceedings{DBLP:conf/iscas/ZhouL07, author = {Dajiang Zhou and Peilin Liu}, title = {A Hardware-Efficient Dual-Standard {VLSI} Architecture for {MC} Interpolation in {AVS} and {H.264}}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20 May 2007, New Orleans, Louisiana, {USA}}, pages = {2910--2913}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/ISCAS.2007.377858}, doi = {10.1109/ISCAS.2007.377858}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/ZhouL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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