BibTeX record conf/iscas/YehCCJ99

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@inproceedings{DBLP:conf/iscas/YehCCJ99,
  author       = {Chingwei Yeh and
                  Min{-}Cheng Chang and
                  Shih{-}Chieh Chang and
                  Wen{-}Ben Jone},
  title        = {Power reduction through iterative gate sizing and voltage scaling},
  booktitle    = {Proceedings of the 1999 International Symposium on Circuits and Systems,
                  {ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
  pages        = {246--249},
  publisher    = {{IEEE}},
  year         = {1999},
  url          = {https://doi.org/10.1109/ISCAS.1999.777849},
  doi          = {10.1109/ISCAS.1999.777849},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/YehCCJ99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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