BibTeX record conf/iscas/YanCLH06

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@inproceedings{DBLP:conf/iscas/YanCLH06,
  author       = {Jin{-}Tai Yan and
                  Yen{-}Hsiang Chen and
                  Chia{-}Fang Lee and
                  Ming{-}Ching Huang},
  title        = {Multilevel timing-constrained full-chip routing in hierarchical quad-grid
                  model},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
                  May 2006, Island of Kos, Greece},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISCAS.2006.1693864},
  doi          = {10.1109/ISCAS.2006.1693864},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/YanCLH06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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