BibTeX record conf/iscas/WengTLY06

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@inproceedings{DBLP:conf/iscas/WengTLY06,
  author       = {Jun{-}Hong Weng and
                  Meng{-}Ting Tsai and
                  Jung{-}Mao Lin and
                  Ching{-}Yuan Yang},
  title        = {A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate
                  clock technique},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
                  May 2006, Island of Kos, Greece},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISCAS.2006.1693274},
  doi          = {10.1109/ISCAS.2006.1693274},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/WengTLY06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}