BibTeX record conf/iscas/Wei-fengYZ05

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@inproceedings{DBLP:conf/iscas/Wei-fengYZ05,
  author       = {Weifeng He and
                  Yunlong Bi and
                  Zhigang Mao},
  title        = {Efficient frame-level pipelined array architecture for full-search
                  block-matching motion estimation},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
                  May 2005, Kobe, Japan},
  pages        = {2887--2890},
  publisher    = {{IEEE}},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCAS.2005.1465230},
  doi          = {10.1109/ISCAS.2005.1465230},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/Wei-fengYZ05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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