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BibTeX record conf/iscas/WangMSC09
@inproceedings{DBLP:conf/iscas/WangMSC09, author = {Li Wang and Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung}, title = {Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17 May 2009, Taipei, Taiwan}, pages = {1293--1296}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/ISCAS.2009.5118000}, doi = {10.1109/ISCAS.2009.5118000}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/WangMSC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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