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BibTeX record conf/iscas/WangBH05
@inproceedings{DBLP:conf/iscas/WangBH05, author = {Yunfeng Wang and Jinian Bian and Xianlong Hong}, title = {Interconnect delay optimization via high level re-synthesis after floorplanning}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26 May 2005, Kobe, Japan}, pages = {5641--5644}, publisher = {{IEEE}}, year = {2005}, url = {https://doi.org/10.1109/ISCAS.2005.1465917}, doi = {10.1109/ISCAS.2005.1465917}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/WangBH05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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