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@inproceedings{DBLP:conf/iscas/VerleMMAA04,
author = {Alexandre Verle and
Xavier Michel and
Philippe Maurine and
Nadine Az{\'e}mard and
Daniel Auvergne},
title = {Delay bound based CMOS gate sizing technique},
booktitle = {ISCAS (5)},
year = {2004},
pages = {189-192},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2005-12-06 by Michael Ley (ley@uni-trier.de)