A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range.

Hyuk-Jun Sung Kwang Sub Yoon A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. 553-556 1999 conf/iscas/1999 ISCAS (2) http://doi.ieeecomputersociety.org/10.1109/ISCAS.1999.780811 db/conf/iscas/iscas1999-2.html#SungY99