Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering.

Jatan P. Shah Rama Sangireddy Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. 4012-4015 2007 conf/iscas/2007 ISCAS http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.378798 db/conf/iscas/iscas2007.html#ShahS07