On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.

Ashoka Visweswara Sathanur Andrea Calimera Antonio Pullini Luca Benini Alberto Macii Enrico Macii Massimo Poncino On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. 2761-2764 2008 ISCAS http://dx.doi.org/10.1109/ISCAS.2008.4542029 conf/iscas/2008 db/conf/iscas/iscas2008.html#SathanurCPBMMP08