BibTeX record conf/iscas/LuWZWH018

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@inproceedings{DBLP:conf/iscas/LuWZWH018,
  author       = {Guangyi Lu and
                  Yuan Wang and
                  Lizhong Zhang and
                  Yize Wang and
                  Ru Huang and
                  Xing Zhang},
  title        = {Investigation on the Gate Bias Voltage of BigFET in Power-rail {ESD}
                  Clamp Circuit for Enhanced Transient Noise Immunity},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
                  27-30 May 2018, Florence, Italy},
  pages        = {1--5},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ISCAS.2018.8350905},
  doi          = {10.1109/ISCAS.2018.8350905},
  timestamp    = {Fri, 18 Oct 2019 12:30:02 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/LuWZWH018.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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