A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.

Hyun-Woo Lee Yong-Hoon Kim Won-Joo Yun Eun Young Park Kang Youl Lee Jaeil Kim Kwang Hyun Kim Jongho Jung Kyung Whan Kim Nam Gyu Rye Kwan-Weon Kim Jun Hyun Chun Chulwoo Kim Young-Jung Choi Byong-Tae Chung Joong Sik Kih A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. 3861-3864 2010 ISCAS http://dx.doi.org/10.1109/ISCAS.2010.5537703 conf/iscas/2010 db/conf/iscas/iscas2010.html#LeeKYPLKKJKRKCKCCK10