BibTeX record conf/iscas/JinT09

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@inproceedings{DBLP:conf/iscas/JinT09,
  author       = {Jie Jin and
                  Chi{-}Ying Tsui},
  title        = {Improving the Hardware Utilization Efficiency of Partially Parallel
                  {LDPC} Decoder with Scheduling and Sub-matrix Decomposition},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17
                  May 2009, Taipei, Taiwan},
  pages        = {2233--2236},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISCAS.2009.5118242},
  doi          = {10.1109/ISCAS.2009.5118242},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/JinT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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