BibTeX record conf/iscas/JiangZSHLLTZLL19

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@inproceedings{DBLP:conf/iscas/JiangZSHLLTZLL19,
  author       = {Haoyun Jiang and
                  Zherui Zhang and
                  Zhengkun Shen and
                  Xiucheng Hao and
                  Zexue Liu and
                  Heyi Li and
                  Yi Tan and
                  Qiang Zhou and
                  Junhua Liu and
                  Huailin Liao},
  title        = {A Calibration-Free Fractional-N {ADPLL} using Retiming Architecture
                  and a 9-bit 0.3ps-INL Phase Interpolator},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
                  Sapporo, Japan, May 26-29, 2019},
  pages        = {1--5},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ISCAS.2019.8702316},
  doi          = {10.1109/ISCAS.2019.8702316},
  timestamp    = {Wed, 07 Dec 2022 23:06:57 +0100},
  biburl       = {https://dblp.org/rec/conf/iscas/JiangZSHLLTZLL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}