Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits.

Masaki Ishida Koichi Hayashi Masakatsu Nishigaki Hideki Asai Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. 411-414 1994 ISCAS db/conf/iscas/iscas1994-1.html#IshidaHNA94