BibTeX record conf/iscas/HsuehCVL08

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@inproceedings{DBLP:conf/iscas/HsuehCVL08,
  author       = {Chih{-}Wen Hsueh and
                  Jen{-}Feng Chung and
                  Lan{-}Da Van and
                  Chin{-}Teng Lin},
  title        = {Anticipatory access pipeline design for phased cache},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
                  May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
  pages        = {2342--2345},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISCAS.2008.4541924},
  doi          = {10.1109/ISCAS.2008.4541924},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/HsuehCVL08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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