A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic.

Baher Haroun Chao Hua Wu A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. 9-12 1994 ISCAS db/conf/iscas/iscas1994-2.html#HarounW94