BibTeX record conf/iscas/Domenech-Asensi23

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@inproceedings{DBLP:conf/iscas/Domenech-Asensi23,
  author       = {Gin{\'{e}}s Dom{\'{e}}nech{-}Asensi and
                  Ram{\'{o}}n Ruiz Merino and
                  Juan Zapata{-}P{\'{e}}rez and
                  Jos{\'{e}} {\'{A}}ngel D{\'{\i}}az{-}Madrid},
  title        = {A 12T {SRAM} in-Memory Computing differential current architecture
                  for {CNN} implementations},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
                  Monterey, CA, USA, May 21-25, 2023},
  pages        = {1--5},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.1109/ISCAS46773.2023.10181992},
  doi          = {10.1109/ISCAS46773.2023.10181992},
  timestamp    = {Mon, 31 Jul 2023 09:05:46 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/Domenech-Asensi23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}