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BibTeX record conf/iscas/ChengHTPC05
@inproceedings{DBLP:conf/iscas/ChengHTPC05, author = {Chih{-}Chi Cheng and Chao{-}Tsung Huang and Po{-}Chih Tseng and Chia{-}Ho Pan and Liang{-}Gee Chen}, title = {Multiple-lifting scheme: memory-efficient {VLSI} implementation for line-based 2-D {DWT}}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26 May 2005, Kobe, Japan}, pages = {5190--5193}, publisher = {{IEEE}}, year = {2005}, url = {https://doi.org/10.1109/ISCAS.2005.1465804}, doi = {10.1109/ISCAS.2005.1465804}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/ChengHTPC05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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