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BibTeX record conf/iscas/ChenTC06
@inproceedings{DBLP:conf/iscas/ChenTC06, author = {Yu{-}Jen Chen and Chen{-}Han Tsai and Liang{-}Gee Chen}, title = {Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in {H.264/AVC}}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24 May 2006, Island of Kos, Greece}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ISCAS.2006.1693161}, doi = {10.1109/ISCAS.2006.1693161}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/ChenTC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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