Area efficient, high speed parallel counter circuits using charge recycling threshold logic.

Peter Celinski Derek Abbott Sorin Dan Cotofana Area efficient, high speed parallel counter circuits using charge recycling threshold logic. 233-236 2003 ISCAS (5) http://dx.doi.org/10.1109/ISCAS.2003.1206239 db/conf/iscas/iscas2003-5.html#CelinskiAC03