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@inproceedings{DBLP:conf/iscas/CelinskiAC03,
author = {Peter Celinski and
Derek Abbott and
Sorin Dan Cotofana},
title = {Area efficient, high speed parallel counter circuits using
charge recycling threshold logic},
booktitle = {ISCAS (5)},
year = {2003},
pages = {233-236},
ee = {http://dx.doi.org/10.1109/ISCAS.2003.1206239},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2006-03-30 by Michael Ley (ley@uni-trier.de)