Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.

Michael Zhang Krste Asanovic Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. 336-345 2005 conf/isca/2005 ISCA http://doi.ieeecomputersociety.org/10.1109/ISCA.2005.53 db/conf/isca/isca2005.html#ZhangA05