Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.

G. Edward Suh Charles W. O'Donnell Ishan Sachdev Srinivas Devadas Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions. 25-36 2005 conf/isca/2005 ISCA http://csdl.computer.org/comp/proceedings/isca/2005/2270/00/22700025abs.htm db/conf/isca/isca2005.html#SuhOSD05