Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors.

Gurindar S. Sohi Sriram Vajapeyam Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 329-336 1998 25 Years ISCA: Retrospectives and Reprints http://doi.acm.org/10.1145/285930.285992 db/conf/isca/reprints98.html#SohiV98