BibTeX record conf/isca/HrishikeshBKSJF02

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@inproceedings{DBLP:conf/isca/HrishikeshBKSJF02,
  author       = {M. S. Hrishikesh and
                  Doug Burger and
                  Stephen W. Keckler and
                  Premkishore Shivakumar and
                  Norman P. Jouppi and
                  Keith I. Farkas},
  editor       = {Yale N. Patt and
                  Dirk Grunwald and
                  Kevin Skadron},
  title        = {The Optimal Logic Depth Per Pipeline Stage is 6 to 8 {FO4} Inverter
                  Delays},
  booktitle    = {29th International Symposium on Computer Architecture {(ISCA} 2002),
                  25-29 May 2002, Anchorage, AK, {USA}},
  pages        = {14--24},
  publisher    = {{IEEE} Computer Society},
  year         = {2002},
  url          = {https://doi.org/10.1109/ISCA.2002.1003558},
  doi          = {10.1109/ISCA.2002.1003558},
  timestamp    = {Fri, 24 Mar 2023 00:02:38 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/HrishikeshBKSJF02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}