An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads.

Hiroaki Hirata Kozo Kimura Satoshi Nagamine Yoshiyuki Mochizuki Akio Nishimura Yoshimori Nakase Teiji Nishizawa An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. 136-145 1992 ISCA db/conf/isca/isca92.html#HirataKNMNNN92