BibTeX record conf/isca/ChenXLSGLLHLCLP20

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@inproceedings{DBLP:conf/isca/ChenXLSGLLHLCLP20,
  author       = {Chen Chen and
                  Xiaoyan Xiang and
                  Chang Liu and
                  Yunhai Shang and
                  Ren Guo and
                  Dongqi Liu and
                  Yimin Lu and
                  Ziyi Hao and
                  Jiahui Luo and
                  Zhijian Chen and
                  Chunqiang Li and
                  Yu Pu and
                  Jianyi Meng and
                  Xiaolang Yan and
                  Yuan Xie and
                  Xiaoning Qi},
  title        = {Xuantie-910: {A} Commercial Multi-Core 12-Stage Pipeline Out-of-Order
                  64-bit High Performance {RISC-V} Processor with Vector Extension :
                  Industrial Product},
  booktitle    = {47th {ACM/IEEE} Annual International Symposium on Computer Architecture,
                  {ISCA} 2020, Virtual Event / Valencia, Spain, May 30 - June 3, 2020},
  pages        = {52--64},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISCA45697.2020.00016},
  doi          = {10.1109/ISCA45697.2020.00016},
  timestamp    = {Tue, 13 Aug 2024 08:01:16 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/ChenXLSGLLHLCLP20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}