A Scalable VLSI Architecture for Binary Prefix Sums.

Rong Lin Koji Nakano Stephan Olariu Maria Cristina Pinotti James L. Schwing Albert Y. Zomaya A Scalable VLSI Architecture for Binary Prefix Sums. 333-337 1998 IPPS/SPDP http://csdl.computer.org/dl/proceedings/ipps/1998/8403/00/84030333.pdf db/conf/ipps/ipps1998.html#LinNOPSZ98