A Technique to Reduce Power and Test Application Time in BIST.

Debjyoti Ghosh Swarup Bhunia Kaushik Roy A Technique to Reduce Power and Test Application Time in BIST. 182-183 2004 conf/iolts/2004 IOLTS http://doi.ieeecomputersociety.org/10.1109/IOLTS.2004.11 db/conf/iolts/iolts2004.html#GhoshBR04