BibTeX record conf/ieeehpcs/SchonbergerH15

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@inproceedings{DBLP:conf/ieeehpcs/SchonbergerH15,
  author       = {Alex Sch{\"{o}}nberger and
                  Klaus Hofmann},
  title        = {Analysis of asymmetric 3D {DRAM} architecture in combination with
                  {L2} cache size reduction},
  booktitle    = {2015 International Conference on High Performance Computing {\&}
                  Simulation, {HPCS} 2015, Amsterdam, Netherlands, July 20-24, 2015},
  pages        = {123--128},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/HPCSim.2015.7237030},
  doi          = {10.1109/HPCSIM.2015.7237030},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/ieeehpcs/SchonbergerH15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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