A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation.

Lijun Li Carl Tropper A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation. 438-445 2008 ICPP http://dx.doi.org/10.1109/ICPP.2008.89 conf/icpp/2008 db/conf/icpp/icpp2008.html#LiT08