An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip.

Akira Yamawaki Masahiko Iwane An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip. 1-8 2007 ICPADS http://doi.ieeecomputersociety.org/10.1109/ICPADS.2007.4447729 conf/icpads/2007 db/conf/icpads/icpads2007.html#YamawakiI07