BibTeX record conf/iciis/AsatiC08

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@inproceedings{DBLP:conf/iciis/AsatiC08,
  author       = {Abhijit R. Asati and
                  Chandrashekhar},
  title        = {An improved high speed fully pipelined 500 MHz 8{\texttimes}8 baugh
                  wooley multiplier design using 0.6 {\(\mu\)}m {CMOS} {TSPC} logic
                  design style},
  booktitle    = {{IEEE} Reglon 10 Colloquium and Third International Conference on
                  Industrial and Information Systems, {ICIIS} 2008, Kharagpur, India,
                  December 8-10, 2008},
  pages        = {1--6},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ICIINFS.2008.4798406},
  doi          = {10.1109/ICIINFS.2008.4798406},
  timestamp    = {Wed, 27 Oct 2021 14:52:42 +0200},
  biburl       = {https://dblp.org/rec/conf/iciis/AsatiC08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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