A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.

Yunfeng Wang Jinian Bian Xianlong Hong Liu Yang Qiang Zhou Qiang Wu A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. 275-286 2005 conf/icess/2005 ICESS http://dx.doi.org/10.1007/11599555_28 db/conf/icess/icess2005.html#WangBHYZW05