BibTeX record conf/icecsys/Schat06

download as .bib file

@inproceedings{DBLP:conf/icecsys/Schat06,
  author       = {Jan Schat},
  title        = {Simulation of SoCs with embedded mixed-signal Cores using a Verilog
                  High-Speed Virtual Serial Interface},
  booktitle    = {13th {IEEE} International Conference on Electronics, Circuits, and
                  Systems, {ICECS} 2006, Nice, France, December 10-13, 2006},
  pages        = {878--881},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ICECS.2006.379929},
  doi          = {10.1109/ICECS.2006.379929},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/icecsys/Schat06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.