BibTeX record conf/icecsys/CasseauL96

download as .bib file

@inproceedings{DBLP:conf/icecsys/CasseauL96,
  author       = {Emmanuel Casseau and
                  Eric L{\"{u}}thi},
  title        = {Architecture of a high-rate {VLSI} Viterbi decoder},
  booktitle    = {Proceedings of Third International Conference on Electronics, Circuits,
                  and Systems, {ICECS} 1996, Rodos, Greece, October 13-16, 1996},
  pages        = {21--24},
  publisher    = {{IEEE}},
  year         = {1996},
  url          = {https://doi.org/10.1109/ICECS.1996.582635},
  doi          = {10.1109/ICECS.1996.582635},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/icecsys/CasseauL96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.