A VLSI array architecture with dynamic frequency clocking.

N. Ranganathan Narayanan Vijaykrishnan N. Bhavanishankar A VLSI array architecture with dynamic frequency clocking. 137-140 1996 conf/iccd/1996 ICCD http://computer.org/proceedings/iccd/7554/75540137abs.htm db/conf/iccd/iccd1996.html#RanganathanVB96