Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses.

Jiangjiang Liu Krishnan Sundaresan Nihar R. Mahapatra Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. 2006 conf/iccd/2006 ICCD http://www.iccd-conference.org/proceedings/2006/paper_228.pdf db/conf/iccd/iccd2006.html#LiuSM06